RISC-V for Soft-core Processor in FPGA
Sorry for the long hiatus in this blog. Life has been hectic in the past 12 months, and blog time is more and more a scarce resource for me. But I think from time to time, it is always necessary to step back and do some reckoning.
One thing I spent plenty of time on was the RISC-V architecture. I learned the name of RISC-V in the middle of last year, and it has really piqued my interest. RISC-V is a sanguine ISA that comes out at a time when ARM’s Cortex M processors were swarming left and right in the embedded world. RISC-V by itself is a nitty design, and it has avoided a lot of pitfalls that other early pioneers fell for. In fact, I think RISC-V could have great potential in the FPGA as a soft-core processor for the following reasons:
1. FPGA is one of the few places that ARM has not fully cracked yet. ARM made an early attempt into the FPGA world through its Cortex M1 processor, and flopped not long after its debut.
2. And at this point of time, ARM has made the source code for its Cortex M0/M3 available to the public, but only a limited few truly adapted ARM as a soft-core in the FPGA.
3. ARM’s failure in the FPGA world might be attributed to
a) Its royalty model
b) Its openness. Although its source code is available through ARM’s DesignStart program, the core portion of it is actually obfuscated.
c) Its sizing. The size of the ARM core is also too big for low end FPGAs
d) JTAG and ways for debug. As in FPGA, the JTAG is not open to 3rd party soft-core processor, extra pins have to be allocated to create a second JTAG port for code download and debug. A big turn-off for many adopters.
4. So the status quo right now is that the soft-core processors for FPGA is largely segmented by the FPGA vendor, for which Xilinx has the Micro-Blaze while Intel has the NIOS II. The headache is that the portability is really an issue if one decides to switch FPGA platforms later.
And RISC-V can certainly be a good alternative to ARM or FPGA vendor’s solution, as RISC-V can enjoy the following good traits:
1. It can cost significantly less than the ARM
2. It can be 100% open source
3. Portability and Flexibility
(To be continued …)
Today's Daily Deal from Apress
Building Embedded Systems
Also available in GBP and CHF*
Unlike SVN, GIT does not have the concept of external property. The closest it has is something called submodules. And here is the steps I took to create submodules:
*) Clone the repository
*) under local copy, create a folder called "submodules"
*) put any file, such as abc.txt under submodules
*) add abc.txt to the repository, and commit it. GIT does not support empty folders. This file will be used to circumvent this rule before we add links to the real submodules
*) open a cygwin windows, enter the submodules folder we created early
*) type in git submodule add URL, where the URL is the path to the submodule repository
*) Use tortoiseGit to switch the submodule to the tag or branch we want
*) delete abc.txt from the repository
To check out, do the following:
*) clone the top repository
git clone URL_to_top_repository
*) At this point, all submodule links are empty, and they need to be updated:
git submodule update --init --recursive
And after you've been working on the repository, you might need to point your submodules to some new tags. This can be done as following:
git submodule update --remote --recursive
And then go to the specific submodule, use tortoiseGit to switch to the right tag.
To make sure the submodules are pointing to the right snapshot, use
git submodule status
to display the SHA-1 value of each submodule, and compare them against those SHA-1 values of the expected tags.
How to Build a Lego Monster Truck
This shield along does not have the Arduino stackable header and screw terminals (3.5mm pitch). To make the procurement job easy, you could get the Ardumoto Shield Kit instead
Update on 10/11/2017
: Sparkfun just came out with a new Ardumoto shield (DEV-14129
) to replace the old one used in this project (DEV-09815
). The difference between those two versions are:
a) The pin assignments are different. The new one uses pin 2 and pin 4 to control the rotation direction, while the old one uses pin 12 and 13
b) The new one added some LEDs with 1K ohm resistors on the IO pins directly to show signal activity. However, this will cause problems for the M10 board. Because the M10 board supports dual voltage IO (3.3V/5V), so the IO output for M10 boards are OD (open drain) instead of totem pole. And the 1K ohm resistor on the new shield will pull the voltage below its threshold. So to use the new shield for this project, those 1K ohm resistors have to be removed.
3) Get the Sparkfun ESP8266 Shield
solder the connector pin head
PWM shield needs a 5V input, that can be provided by wiring the 5V pin
on ESP8266 shield to the power connector of PWM shield, and stack them together, like the
4) Get Two DC 3V-6V Dual Axis Gear Motor from banggood.com. Or t
hey might cost less than $1 each if you buy them from AliExpress
solder wires to the DC motor with 22AWG solid core
5) build the steering mechanism:
6) Hack one of the DC motors according to instructions here
, and attach it to the Lego Gear Box
7) Mount the steering mechanism and the DC motor to a Lego 8 x 16 plate using cable tie
Attach the other DC motor with two wheels. The wheels are 65 mm in
diameter and 28 mm wide. You can get them from Amazon or banggood.com
9) Attach the DC motors (with wheels) to 3 2 x 16 Lego Plate stack
10) put everything above together with cable tie, connect the DC motor to PWM shield
Now you get yourself a Lego Monster Truck. And stay tuned for firmware/software!
PulseRain M10 board has officially entered the race for HackadayPrize2017! as "Play FPGA with Arduino"
The project page is
And for readers of this blog, please do me a favor by clicking the "Like Project" button on this page. (If you have a GitHub or Twitter account, you can sign in directly.). To tell you the truth, every like this project receives will translate into $1.00 seed money with $200 ceiling. Wow, that can buy hundreds of cups of mid-night coffee!
PulseRain M10: A FPGA Board like No Other
People start asking me why this blog had a long hiatus. And here is what's happening
My coworkers and I have spent the better part of the past 5 months developing and fine-tuning PulseRain's latest product: The M10 FPGA board.
We chose to make the M10 board because we need a platform to verify our FP51-1T MCU core. The FP51-1T is an 8051 core that has single clock instruction cycle. It has 4 stage pipeline structure that can reach above 100MHz on Altera Max10 C8 speed grade device. A lot of open source 8051 core claim to be 1T instruction cycle, but they often fall short on FMAX (max clock frequency). Most of them will fold around 50 - 60 MHz for the C8 speed grade.
And for the FPGA platform we are looking for, we would like to see:
*) open source hardware
*) versatile with plenty of peripherals
*) software friendly
We have looked up and down, but couldn't find a perfect match yet. So we decided to go extra miles and do it by ourselves.
And a spy photo of this board can be found here
We original decided on the name Mustang Duino, but later we took some marketing advice and named it PulseRain M10, because:
A) It has an Altera MAX 10 FPGA on board. On the record, M is for MAX
B) Internally, we nickname FP51 as Mustang to honor the legendary Mustang Fighter-bomber in World War II. So off the record, M stands for Mustang.:-)
We made the form factor of this board to be Arduino compatible, and we support both 3.3V and 5V IO through jumper setting, so that both 3.3V and 5V shield can be mounted to our board. By itself, the board is 2.1 inch x 3.2 inch.
And the board has an Altera 10M08SAE144C8G FPGA, with onboard peripherals like
*) Temperature Sensing Diode
*) Serial SRAM
*) Voice Codec, (with onboard microphne and speaking plug)
*) MicroSD Card Socket
For more information, please go to m10.pulserain.com
The prototype of the board meets our expectations. And we are currently starting pilot run for production. Stay tuned!
NIOS II Processor in MAX 10 Device
The Altera NIOS II (Gen 2) processor comes with MAX 10 device for free, sort of.
In fact, the NIOS II comes with two flavors: economical and fast. Unfortunately, it seems the latter needs a license while the former is truly free as free beer.
And the MAX 10 has very limited BRAMs. I found it not too hard to make bloated code that devour all the available BRAMs. In particular, please skimp on the usage of printf, and use small size C library if possible.
PS: Warmest Condolences to those who lost their loved ones 15 years ago.
*) Legal Disclaimer
*) The Book
*) FCC Wireless
*) PAPA System