HackadayPrize2017 3/22/2017

PulseRain M10 board has officially entered the race for HackadayPrize2017! as "Play FPGA with Arduino"

The project page is


And for readers of this blog, please do me a favor by clicking the "Like Project" button on this page. (If you have a GitHub or Twitter account, you can sign in directly.). To tell you the truth, every like this project receives will translate into $1.00 seed money with $200 ceiling. Wow, that can buy hundreds of cups of mid-night coffee!

    Posted by Changyi at 9:38 PM 0 Comments  

 PulseRain M10: A FPGA Board like No Other 3/04/2017

People start asking me why this blog had a long hiatus. And here is what's happening

My coworkers and I have spent the better part of the past 5 months developing and fine-tuning PulseRain's latest product: The M10 FPGA board.

We chose to make the M10 board because we need a platform to verify our FP51-1T MCU core. The FP51-1T is an 8051 core that has single clock instruction cycle. It has 4 stage pipeline structure that can reach above 100MHz on Altera Max10 C8 speed grade device. A lot of open source 8051 core claim to be 1T instruction cycle, but they often fall short on FMAX (max clock frequency). Most of them will fold around 50 - 60 MHz for the C8 speed grade.

And for the FPGA platform we are looking for, we would like to see:

*) open source hardware

*) versatile with plenty of peripherals

*) expandable

*) software friendly

*) DFM

We have looked up and down, but couldn't find a perfect match yet. So we decided to go extra miles and do it by ourselves.

And a spy photo of this board can be found here

We original decided on the name Mustang Duino, but later we took some marketing advice and named it PulseRain M10, because:

A) It has an Altera MAX 10 FPGA on board. On the record, M is for MAX

B) Internally, we nickname FP51 as Mustang to honor the legendary Mustang Fighter-bomber in World War II. So off the record, M stands for Mustang.:-)

We made the form factor of this board to be Arduino compatible, and we support both 3.3V and 5V IO through jumper setting, so that both 3.3V and 5V shield can be mounted to our board. By itself, the board is 2.1 inch x 3.2 inch.

And the board has an Altera 10M08SAE144C8G FPGA, with onboard peripherals like

*) ADC
*) Temperature Sensing Diode
*) Serial SRAM
*) Voice Codec, (with onboard microphne and speaking plug)
*) MicroSD Card Socket

For more information, please go to m10.pulserain.com

The prototype of the board meets our expectations. And we are currently starting pilot run for production. Stay tuned!

    Posted by Changyi at 2:03 PM 0 Comments  

 NIOS II Processor in MAX 10 Device 9/11/2016

The Altera NIOS II (Gen 2) processor comes with MAX 10 device for free, sort of.

In fact, the NIOS II comes with two flavors: economical and fast. Unfortunately, it seems the latter needs a license while the former is truly free as free beer.

And the MAX 10 has very limited BRAMs. I found it not too hard to make bloated code that devour all the available BRAMs. In particular, please skimp on the usage of printf, and use small size C library if possible.

PS: Warmest Condolences to those who lost their loved ones 15 years ago.

    Posted by Changyi at 12:32 AM 0 Comments  

 SDC Constraint, Input / Output Delay 8/26/2016

Preparing IO constraint for FPGA is always a tedious job. And the following is a spreadsheet to help the number crunching. BTW, I have to say that MS Excel is much more powerful than Google Spreadsheet.

    Posted by Changyi at 12:54 AM 0 Comments  

 AES and Encryption in China 8/10/2016

AES is a popular encryption algorithm with symmetric keys. If you are looking for open source AES implementions, Ref [1] is one of them.

To verify the AES implementation is in line with National Standard, use the test vectors from Ref[2] as passing criteria.

BTW,  China has its own flavor of encryption product regulation (Ref[3][4][5][6][7]). Ask Office of Security Commercial Code Administration (OSCCA) before the police knocking on your door. I'm not kidding, and HP knows it all well :-( (Ref[3]).

[1] Ilya Levin, a byte-oriented aes-256 implementation
[2] Morris Dworkin, Recommendation for Block Cipher Modes of Operation, Methods and Techniques, NIST, 2001
[3] Xia Yu and Matthew Murphy, The Regulation of Encryption Products in China, MMLC Group
[5] 商用密码产品使用管理规定
[6] Mr.王掌柜, 中国有趣的“商用密码管理”
[7] 个人使用密码产品,例如 OpenSSL,是否属于违法行为?

    Posted by Changyi at 8:58 PM 0 Comments  

 Tab Completion in Python 3 7/16/2016

For CLI (Command Line Interface), tab completion is always a handy feature. Before Python 3, you can use readline package (Ref [1]) to implement tab completion. However, readline became obsolete after Python 3. Fortunately, an alternative solution can be found here. This script is part of PulseRain Technology's FP51 debugger, but it can be applied elsewhere generally.

In addition, serial port often calls for full-duplex. One way to achieve full-duplex is, of course, to use multi-thread. Another way to do this is to use non-block read for UART Rx. This can also be found in OCD_Input.py.

[1] rlcompleter — Completion function for GNU readline

    Posted by Changyi at 2:09 AM 0 Comments  

 Book: Building Embedded Systems 6/30/2016

Changyi Gu,
Building Embedded Systems - Programmable Hardware
APress, 06/2016

This is the first book I have published. I have been a tinker of things for the better part of my life. And the successful launch of this book  has given me the illusion of being capable of tinkering words (Please pardon my naivety.). So now I become a blogger.

This blog is supposed to casually record the itsy-bitsy that I gleaned, in the hope that some of which can be useful to others. As the old saying goes: one man's limerick is another man's clue trail. And please forgive me if the topic is too trivial or awfully naive.

BTW, readers are welcomed to leave comments here regarding my book. But I can not promise I will be able to respond in a timely fashion.

    Posted by Changyi at 1:22 AM 0 Comments  





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