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Lab Notes - Lmutil Kill License
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6/26/2020
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Every engineer needs to make a living, so is every software engineer. And license is an important piece of that big pie. Often times, FLEXlm is used to manage the license.
Occasionally, the license hangs due to crash on the client side. And here is how to kill a zombie license:
Use lmutil stat -a
to find out that hanging license, which includes:
license_name
user_name
license_server_name
port_number on the license server
user_name
user_computer
display
And use the following to remove the hanging license:
lmutil lmremove -c port_num@server_name license_name user_name user_computer display
*) Sometimes "display" is the same as user_computer, sometimes it is just a number. (probably with an underscore in the middle)
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What's Next for VHDL/Verilog?
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5/14/2020
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Running Scala from Windows Batch file (.cmd file)
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5/12/2020
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Scala is by far the most versatile language I have ever seen. And personally, I would use it to replace all the existing script solutions.
To run Scala in Windows batch file (.cmd file), the following can be a good example. It shows how to break a long list of numbers into multiple groups, and print them out in a different format:
::#!
@echo off
set path_name=%~p0
set file_name=%~n0%~x0
pushd %path_name% & scala -cp C:\repo\scala_pkg -deprecation %file_name% %* & popd
::!#
// The true Scala code starts here
object Main {
def main(args : Array[String]) = {
val coef : List[Int] = List (-1, 2, 3, 4, -5, 6, 7, 8, 9, 10, -11, -12, 13, 14, 15, 16, 17, 18, -19, 20)
val coefGroup : List [List[Int]] = coef.grouped(5).toList
val coefStr : List[String] = coefGroup map (_.mkString("(", ", ", ", others => 0),"))
coefStr.foreach(println)
}
}
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Notepad++ updated
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10/31/2019
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Cheers to Notepad++
Finally I've got my update downloaded and installed successfully. As a loyal user of Notepad++, I would like to offer my congratulation for its latest release.
And for those who have got issues, here is a link for them.
BTW, the following is a log from early releases. I think it might still be useful for edification purpose.
Freedom of expression is like the air we breathe, we don't feel it, until people take it away from us.
For this reason, Je suis Charlie, not because I endorse everything they published, but because I cherish the right to speak out freely without risk even when it offends others.
And no, you cannot just take someone's life for whatever he/she expressed.
Hence this "Je suis Charlie" edition.
- #JeSuisCharlie
============================
Notepad++ upgrade log, 01/21/2015
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RISC-V for Soft-core Processor in FPGA
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8/24/2018
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Sorry for the long hiatus in this blog. Life has been hectic in the past 12 months, and blog time is more and more a scarce resource for me. But I think from time to time, it is always necessary to step back and do some reckoning.
One thing I spent plenty of time on was the RISC-V architecture. I learned the name of RISC-V in the middle of last year, and it has really piqued my interest. RISC-V is a sanguine ISA that comes out at a time when ARM’s Cortex M processors were swarming left and right in the embedded world. RISC-V by itself is a nitty design, and it has avoided a lot of pitfalls that other early pioneers fell for. In fact, I think RISC-V could have great potential in the FPGA as a soft-core processor for the following reasons:
1. FPGA is one of the few places that ARM has not fully cracked yet. ARM made an early attempt into the FPGA world through its Cortex M1 processor, and flopped not long after its debut.
2. And at this point of time, ARM has made the source code for its Cortex M0/M3 available to the public, but only a limited few truly adapted ARM as a soft-core in the FPGA.
3. ARM’s failure in the FPGA world might be attributed to
a) Its royalty model
b) Its openness. Although its source code is available through ARM’s DesignStart program, the core portion of it is actually obfuscated.
c) Its sizing. The size of the ARM core is also too big for low end FPGAs
d) JTAG and ways for debug. As in FPGA, the JTAG is not open to 3rd party soft-core processor, extra pins have to be allocated to create a second JTAG port for code download and debug. A big turn-off for many adopters.
4. So the status quo right now is that the soft-core processors for FPGA is largely segmented by the FPGA vendor, for which Xilinx has the Micro-Blaze while Intel has the NIOS II. The headache is that the portability is really an issue if one decides to switch FPGA platforms later.
And RISC-V can certainly be a good alternative to ARM or FPGA vendor’s solution, as RISC-V can enjoy the following good traits:
1. It can cost significantly less than the ARM
2. It can be 100% open source
3. Portability and Flexibility
(To be continued …)
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Today's Daily Deal from Apress
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9/25/2017
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Building Embedded Systems
9.99 USD 39.99 USD
9.99 EUR 35.69 EUR
Also available in GBP and CHF*
Unlike SVN, GIT does not have the concept of external property. The closest it has is something called submodules. And here is the steps I took to create submodules:
*) Clone the repository
*) under local copy, create a folder called "submodules"
*) put any file, such as abc.txt under submodules
*) add abc.txt to the repository, and commit it. GIT does not support empty folders. This file will be used to circumvent this rule before we add links to the real submodules
*) open a cygwin windows, enter the submodules folder we created early
*) type in git submodule add URL, where the URL is the path to the submodule repository
*) Use tortoiseGit to switch the submodule to the tag or branch we want
*) delete abc.txt from the repository
*) commit
To check out, do the following:
*) clone the top repository
git clone URL_to_top_repository
*) At this point, all submodule links are empty, and they need to be updated:
git submodule update --init --recursive
And after you've been working on the repository, you might need to point your submodules to some new tags. This can be done as following:
git submodule update --remote --recursive
And then go to the specific submodule, use tortoiseGit to switch to the right tag.
To make sure the submodules are pointing to the right snapshot, use
git submodule status
to display the SHA-1 value of each submodule, and compare them against those SHA-1 values of the expected tags.
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*) Legal Disclaimer
*) The Book
*) PulseRain
*) FPGA Limerick
*) GitHub
*) Forum
*) FCC Wireless
*) ARRL
*) PAPA System
*) EARS
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